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32 commits

Author SHA1 Message Date
babbleberry
d70738eea6 Updated to add -mstrict-align and use Apple Silicon gcc 2024-04-22 10:50:24 +01:00
babbleberry
71d96e9044 Fixed pull up/pull down being the wrong way around 2024-04-22 09:54:15 +01:00
Adam Greenwood-Byrne
1d022a6b6c
Revert "Solve Issue #50 pull up pull down register mapping wrong way around" 2024-04-22 09:49:39 +01:00
Nelson Ehling
c71a1cc18a Merge branch 'master' of https://github.com/LabNelson/rpi4-osdev 2024-03-27 12:51:32 +01:00
Nelson Ehling
d7ad289e54 setup folder for interrupt controlled SPI-Ethernet 2024-03-27 12:35:12 +01:00
Nelson Ehling
8277e48bc2 changed pull up pull down register mapping 2024-03-20 14:51:11 +01:00
isometimes
2b9e41259b Fix SI units 2022-07-05 18:05:42 +01:00
isometimes
9716f950b8 Added other backlinks 2022-07-05 12:15:30 +01:00
Adam Greenwood-Byrne
66f80328bc Fixed fb.c across the board, iterated on Ethernet support - still WIP 2021-10-26 09:50:13 +01:00
Adam Greenwood-Byrne
888398be2e Fixed typo 2021-08-30 15:37:44 +01:00
Adam Greenwood-Byrne
ca88bcaa0b Added warning about firmware regression to part10-multicore 2021-08-30 15:36:40 +01:00
isometimes
5c5fb1493e Fixed nostartfiles issue with Makefile.gcc* as ld no longer ignores erroneous arguments 2021-08-27 11:56:23 +01:00
Adam Greenwood-Byrne
5279a69e34 Uploading multi-core version of Breakout as part11 2021-02-24 20:02:43 +00:00
Adam Greenwood-Byrne
1bd5a7da8b Finished part10 write-up 2021-02-23 17:24:00 +00:00
Adam Greenwood-Byrne
50e967b1c8 Added images to part10 2021-02-23 17:04:24 +00:00
Adam Greenwood-Byrne
c721e6405f Finalised visuals for part10 2021-02-23 16:27:12 +00:00
Adam Greenwood-Byrne
89f33b4b83 Added third core doing something now 2021-02-23 16:23:53 +00:00
Adam Greenwood-Byrne
84f7ebfae8 Added better progress indicators for the cores in kernel.c 2021-02-23 15:33:12 +00:00
Adam Greenwood-Byrne
0e540533d9 Removed unnecessary alignment directives in link.ld 2021-02-23 12:25:40 +00:00
Adam Greenwood-Byrne
44669ee990 Fixed typo 2021-02-23 12:23:48 +00:00
Adam Greenwood-Byrne
995bc2a522 Each core now has its own designated stack 2021-02-23 12:22:59 +00:00
Adam Greenwood-Byrne
7884f5f3bb Final part10 doc changes for today 2021-02-22 23:14:03 +00:00
Adam Greenwood-Byrne
30947d8b0c Updated to part10 docs 2021-02-22 23:09:34 +00:00
Adam Greenwood-Byrne
6cc15d3b9b Added more documention to the multicore example in part10 2021-02-22 23:03:17 +00:00
Adam Greenwood-Byrne
295be0cc57 Doc update for part10-multicore 2021-02-22 12:15:47 +00:00
Adam Greenwood-Byrne
d5fcab0694 Now setting DMA transfer on CPU core 2 to show both cores free 2021-02-22 12:09:11 +00:00
Adam Greenwood-Byrne
75beaecccf Cleaned up boot.S so it's clearer where the changes are from part9 2021-02-22 11:28:55 +00:00
Adam Greenwood-Byrne
56068acbb6 Demonstrating running on both core1 and core2 now 2021-02-22 10:32:24 +00:00
Adam Greenwood-Byrne
e0b0076abc Fixed a typo in the write-up 2021-02-22 10:25:12 +00:00
Adam Greenwood-Byrne
24cde45119 Slimmed down the muilticore example 2021-02-22 10:24:12 +00:00
Adam Greenwood-Byrne
e409b722b9 A few short changes to the write-up 2021-02-21 21:47:59 +00:00
Adam Greenwood-Byrne
65560deb5a Added part10-multicore - a rough multicore approach to sound 2021-02-21 20:58:04 +00:00