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https://github.com/isometimes/rpi4-osdev
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Slimmed down the muilticore example
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e409b722b9
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7 changed files with 32 additions and 87 deletions
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@ -17,9 +17,9 @@ arm_64bit=1
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For now, I'll signpost the following points of interest in the code:
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* The new _boot.S_ loader and related _boot.h_ header
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* The new _boot.S_ loader
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* The new _multicore.c_ library and related _multicore.h_ header
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* A slimmed down _io.h_ and _kernel.c_ (DMA sound removed), with a new multicore approach to `main()`
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* A revised _link.ld_ adding provisions for the secondary core's stack and the 0x00000 entry point (a result of setting `kernel_old=1`
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* A revised _link.ld_ adding provisions for a secondary core's stack and the 0x00000 entry point (a result of setting `kernel_old=1`
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I will write more soon to attempt to explain what's going on here.
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@ -1,35 +1,21 @@
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#include "boot.h"
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#define LOCAL_CONTROL 0xff800000
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#define LOCAL_PRESCALER 0xff800008
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#define OSC_FREQ 54000000
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#define MAIN_STACK 0x400000
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.section ".text.boot"
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.globl _start
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_start:
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ldr x0, =SCTLR_VALUE_MMU_DISABLED
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msr sctlr_el1, x0
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ldr x0, =LOCAL_CONTROL
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ldr x0, =LOCAL_CONTROL // Sort out the timer
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str wzr, [x0]
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mov w1, 0x80000000
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str w1, [x0, #(LOCAL_PRESCALER - LOCAL_CONTROL)]
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ldr x0, =OSC_FREQ // Sort out the timer
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ldr x0, =OSC_FREQ
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msr cntfrq_el0, x0
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msr cntvoff_el2, xzr
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ldr x0, =HCR_VALUE
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msr hcr_el2, x0
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ldr x0, =SCR_VALUE
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msr scr_el3, x0
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ldr x0, =SPSR_VALUE
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msr spsr_el3, x0
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adr x0, in_el2
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msr elr_el3, x0
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eret
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in_el2:
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mrs x6, mpidr_el1
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and x6, x6,#0xFF // Check processor id
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cbz x6, primary_cpu // Hang for all non-primary CPU
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@ -40,12 +26,10 @@ proc_hang:
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ldr x4, [x5, x6, lsl #3]
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cbz x4, proc_hang
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mov x0, #0
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str x0, [x5, x6, lsl #3] // Zero the address again
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ldr x1, =__test_stack // Get ourselves a fresh stack
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mov sp, x1
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boot_kernel:
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secondary_cpu:
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mov x0, #0
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mov x1, #0
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mov x2, #0
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mov x3, #0
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@ -60,7 +44,7 @@ memzero:
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sub w2, w2, #1
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cbnz w2, memzero
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startup:
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mov sp, #LOW_MEMORY
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mov sp, #MAIN_STACK
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bl main
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b proc_hang // should never come here
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@ -1,58 +0,0 @@
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// ***************************************
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// SCTLR_EL1, System Control Register (EL1), Page 2654 of AArch64-Reference-Manual.
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// ***************************************
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#define SCTLR_RESERVED (3 << 28) | (3 << 22) | (1 << 20) | (1 << 11)
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#define SCTLR_EE_LITTLE_ENDIAN (0 << 25)
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#define SCTLR_EOE_LITTLE_ENDIAN (0 << 24)
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#define SCTLR_I_CACHE_DISABLED (0 << 12)
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#define SCTLR_D_CACHE_DISABLED (0 << 2)
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#define SCTLR_MMU_DISABLED (0 << 0)
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#define SCTLR_MMU_ENABLED (1 << 0)
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#define SCTLR_VALUE_MMU_DISABLED (SCTLR_RESERVED | SCTLR_EE_LITTLE_ENDIAN | SCTLR_I_CACHE_DISABLED | SCTLR_D_CACHE_DISABLED | SCTLR_MMU_DISABLED)
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// ***************************************
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// HCR_EL2, Hypervisor Configuration Register (EL2), Page 2487 of AArch64-Reference-Manual.
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// ***************************************
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#define HCR_RW (1 << 31)
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#define HCR_VALUE HCR_RW
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// ***************************************
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// SCR_EL3, Secure Configuration Register (EL3), Page 2648 of AArch64-Reference-Manual.
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// ***************************************
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#define SCR_RESERVED (3 << 4)
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#define SCR_RW (1 << 10)
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#define SCR_NS (1 << 0)
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#define SCR_VALUE (SCR_RESERVED | SCR_RW | SCR_NS)
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// ***************************************
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// SPSR_EL3, Saved Program Status Register (EL3) Page 389 of AArch64-Reference-Manual.
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// ***************************************
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#define SPSR_MASK_ALL (7 << 6)
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#define SPSR_EL1h (5 << 0)
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#define SPSR_VALUE (SPSR_MASK_ALL | SPSR_EL1h)
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// ***************************************
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// Memory management stuff
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// ***************************************
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#define PAGE_SHIFT 12
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#define TABLE_SHIFT 9
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#define SECTION_SHIFT (PAGE_SHIFT + TABLE_SHIFT)
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#define PAGE_SIZE (1 << PAGE_SHIFT)
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#define SECTION_SIZE (1 << SECTION_SHIFT)
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#define LOW_MEMORY (2 * SECTION_SIZE) // 0x400000
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// ***************************************
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// Timer stuff
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// ***************************************
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#define LOCAL_CONTROL 0xff800000
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#define LOCAL_PRESCALER 0xff800008
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#define OSC_FREQ 54000000
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@ -94,6 +94,8 @@ void playaudio_cpu()
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void core1_main(void)
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{
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clear_core1(); // Only run once
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debugstr("Playing on CPU Core #1... ");
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playaudio_cpu();
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debugstr(" done"); debugcrlf();
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@ -17,8 +17,8 @@ SECTIONS
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. = ALIGN(16);
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. = . + 512;
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__test_stack = .;
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*(.testStack)
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}
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_end = .;
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/DISCARD/ : { *(.comment) *(.gnu*) *(.note*) *(.eh_frame*) }
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}
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@ -27,3 +27,18 @@ void start_core3(void (*func)(void))
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store32((unsigned long)&spin_cpu3, (unsigned long)func);
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asm volatile ("sev");
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}
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void clear_core1(void)
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{
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store32((unsigned long)&spin_cpu1, 0);
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}
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void clear_core2(void)
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{
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store32((unsigned long)&spin_cpu2, 0);
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}
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void clear_core3(void)
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{
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store32((unsigned long)&spin_cpu3, 0);
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}
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@ -3,7 +3,9 @@ extern unsigned int spin_cpu1;
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extern unsigned int spin_cpu2;
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extern unsigned int spin_cpu3;
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unsigned long load32(unsigned long address);
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void start_core1(void (*func)(void));
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void start_core2(void (*func)(void));
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void start_core3(void (*func)(void));
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void clear_core1(void);
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void clear_core2(void);
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void clear_core3(void);
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