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Slimmed down the muilticore example

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Adam Greenwood-Byrne 2021-02-22 10:24:12 +00:00
parent e409b722b9
commit 24cde45119
7 changed files with 32 additions and 87 deletions
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4
part10-multicore/README.md
View file

@ -17,9 +17,9 @@ arm_64bit=1
For now, I'll signpost the following points of interest in the code:
* The new _boot.S_ loader and related _boot.h_ header
* The new _boot.S_ loader
* The new _multicore.c_ library and related _multicore.h_ header
* A slimmed down _io.h_ and _kernel.c_ (DMA sound removed), with a new multicore approach to `main()`
* A revised _link.ld_ adding provisions for the secondary core's stack and the 0x00000 entry point (a result of setting `kernel_old=1`
* A revised _link.ld_ adding provisions for a secondary core's stack and the 0x00000 entry point (a result of setting `kernel_old=1`
I will write more soon to attempt to explain what's going on here.

34
part10-multicore/boot.S
View file

@ -1,35 +1,21 @@
#include "boot.h"
#define LOCAL_CONTROL 0xff800000
#define LOCAL_PRESCALER 0xff800008
#define OSC_FREQ 54000000
#define MAIN_STACK 0x400000
.section ".text.boot"
.globl _start
_start:
ldr x0, =SCTLR_VALUE_MMU_DISABLED
msr sctlr_el1, x0
ldr x0, =LOCAL_CONTROL
ldr x0, =LOCAL_CONTROL // Sort out the timer
str wzr, [x0]
mov w1, 0x80000000
str w1, [x0, #(LOCAL_PRESCALER - LOCAL_CONTROL)]
ldr x0, =OSC_FREQ // Sort out the timer
ldr x0, =OSC_FREQ
msr cntfrq_el0, x0
msr cntvoff_el2, xzr
ldr x0, =HCR_VALUE
msr hcr_el2, x0
ldr x0, =SCR_VALUE
msr scr_el3, x0
ldr x0, =SPSR_VALUE
msr spsr_el3, x0
adr x0, in_el2
msr elr_el3, x0
eret
in_el2:
mrs x6, mpidr_el1
and x6, x6,#0xFF // Check processor id
cbz x6, primary_cpu // Hang for all non-primary CPU
@ -40,12 +26,10 @@ proc_hang:
ldr x4, [x5, x6, lsl #3]
cbz x4, proc_hang
mov x0, #0
str x0, [x5, x6, lsl #3] // Zero the address again
ldr x1, =__test_stack // Get ourselves a fresh stack
mov sp, x1
boot_kernel:
secondary_cpu:
mov x0, #0
mov x1, #0
mov x2, #0
mov x3, #0
@ -60,7 +44,7 @@ memzero:
sub w2, w2, #1
cbnz w2, memzero
startup:
mov sp, #LOW_MEMORY
mov sp, #MAIN_STACK
bl main
b proc_hang // should never come here

58
part10-multicore/boot.h
View file

@ -1,58 +0,0 @@
// ***************************************
// SCTLR_EL1, System Control Register (EL1), Page 2654 of AArch64-Reference-Manual.
// ***************************************
#define SCTLR_RESERVED (3 << 28) | (3 << 22) | (1 << 20) | (1 << 11)
#define SCTLR_EE_LITTLE_ENDIAN (0 << 25)
#define SCTLR_EOE_LITTLE_ENDIAN (0 << 24)
#define SCTLR_I_CACHE_DISABLED (0 << 12)
#define SCTLR_D_CACHE_DISABLED (0 << 2)
#define SCTLR_MMU_DISABLED (0 << 0)
#define SCTLR_MMU_ENABLED (1 << 0)
#define SCTLR_VALUE_MMU_DISABLED (SCTLR_RESERVED | SCTLR_EE_LITTLE_ENDIAN | SCTLR_I_CACHE_DISABLED | SCTLR_D_CACHE_DISABLED | SCTLR_MMU_DISABLED)
// ***************************************
// HCR_EL2, Hypervisor Configuration Register (EL2), Page 2487 of AArch64-Reference-Manual.
// ***************************************
#define HCR_RW (1 << 31)
#define HCR_VALUE HCR_RW
// ***************************************
// SCR_EL3, Secure Configuration Register (EL3), Page 2648 of AArch64-Reference-Manual.
// ***************************************
#define SCR_RESERVED (3 << 4)
#define SCR_RW (1 << 10)
#define SCR_NS (1 << 0)
#define SCR_VALUE (SCR_RESERVED | SCR_RW | SCR_NS)
// ***************************************
// SPSR_EL3, Saved Program Status Register (EL3) Page 389 of AArch64-Reference-Manual.
// ***************************************
#define SPSR_MASK_ALL (7 << 6)
#define SPSR_EL1h (5 << 0)
#define SPSR_VALUE (SPSR_MASK_ALL | SPSR_EL1h)
// ***************************************
// Memory management stuff
// ***************************************
#define PAGE_SHIFT 12
#define TABLE_SHIFT 9
#define SECTION_SHIFT (PAGE_SHIFT + TABLE_SHIFT)
#define PAGE_SIZE (1 << PAGE_SHIFT)
#define SECTION_SIZE (1 << SECTION_SHIFT)
#define LOW_MEMORY (2 * SECTION_SIZE) // 0x400000
// ***************************************
// Timer stuff
// ***************************************
#define LOCAL_CONTROL 0xff800000
#define LOCAL_PRESCALER 0xff800008
#define OSC_FREQ 54000000

2
part10-multicore/kernel.c
View file

@ -94,6 +94,8 @@ void playaudio_cpu()
void core1_main(void)
{
clear_core1(); // Only run once
debugstr("Playing on CPU Core #1... ");
playaudio_cpu();
debugstr(" done"); debugcrlf();

2
part10-multicore/link.ld
View file

@ -17,8 +17,8 @@ SECTIONS
. = ALIGN(16);
. = . + 512;
__test_stack = .;
*(.testStack)
}
_end = .;
/DISCARD/ : { *(.comment) *(.gnu*) *(.note*) *(.eh_frame*) }
}

15
part10-multicore/multicore.c
View file

@ -27,3 +27,18 @@ void start_core3(void (*func)(void))
store32((unsigned long)&spin_cpu3, (unsigned long)func);
asm volatile ("sev");
}
void clear_core1(void)
{
store32((unsigned long)&spin_cpu1, 0);
}
void clear_core2(void)
{
store32((unsigned long)&spin_cpu2, 0);
}
void clear_core3(void)
{
store32((unsigned long)&spin_cpu3, 0);
}

4
part10-multicore/multicore.h
View file

@ -3,7 +3,9 @@ extern unsigned int spin_cpu1;
extern unsigned int spin_cpu2;
extern unsigned int spin_cpu3;
unsigned long load32(unsigned long address);
void start_core1(void (*func)(void));
void start_core2(void (*func)(void));
void start_core3(void (*func)(void));
void clear_core1(void);
void clear_core2(void);
void clear_core3(void);