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https://github.com/isometimes/rpi4-osdev
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Now setting DMA transfer on CPU core 2 to show both cores free
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commit
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2 changed files with 84 additions and 9 deletions
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@ -1,4 +1,6 @@
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#define PERIPHERAL_BASE 0xFE000000
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#define LEGACY_BASE 0x7E000000
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#define SAFE_ADDRESS 0x00400000 // Somewhere safe to store a lot of data
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void uart_init();
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void uart_writeText(char *buffer);
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@ -3,7 +3,10 @@
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#include "multicore.h"
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#define PWM_BASE (PERIPHERAL_BASE + 0x20C000 + 0x800) /* PWM1 register base address on RPi4 */
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#define PWM_LEGACY_BASE (LEGACY_BASE + 0x20C000 + 0x800) /* PWM1 register base legacy address on RPi4 */
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#define CLOCK_BASE (PERIPHERAL_BASE + 0x101000)
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#define DMA_BASE (PERIPHERAL_BASE + 0x007100) /* DMA register base address */
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#define DMA_ENABLE (DMA_BASE + 0xFF0) /* DMA global enable bits */
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#define BCM2711_PWMCLK_CNTL 40
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#define BCM2711_PWMCLK_DIV 41
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@ -31,8 +34,71 @@
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#define BCM2711_FULL1 0x1
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#define ERRORMASK (BCM2711_GAPO2 | BCM2711_GAPO1 | BCM2711_RERR1 | BCM2711_WERR1)
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#define DMA_CS 0 /* Control/status register offset for DMA channel 0 */
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#define DMA_CONBLK_AD 1
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#define DMA_EN1 1 << 1 /* Enable DMA engine 1 */
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#define DMA_ACTIVE 1 /* Active bit set */
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#define DMA_DEST_DREQ 0x40 /* Use DREQ to pace peripheral writes */
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#define DMA_PERMAP_1 0x10000 /* PWM1 peripheral for DREQ */
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#define DMA_SRC_INC 0x100 /* Increment source address */
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volatile unsigned* clk = (void*)CLOCK_BASE;
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volatile unsigned* pwm = (void*)PWM_BASE;
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volatile unsigned* dma = (void*)DMA_BASE;
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volatile unsigned* dmae = (void*)DMA_ENABLE;
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volatile unsigned* safe = (void*)SAFE_ADDRESS;
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struct dma_cb {
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unsigned int ti;
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unsigned int source_ad;
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unsigned int dest_ad;
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unsigned int txfr_len;
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unsigned int stride;
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unsigned int nextconbk;
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unsigned int null1;
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unsigned int null2;
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} __attribute__((aligned(32)));
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struct dma_cb playback_cb;
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static void playaudio_dma(void)
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{
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extern unsigned char _binary_audio_bin_start[];
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extern unsigned char _binary_audio_bin_size[];
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unsigned int size = (long)&_binary_audio_bin_size;
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unsigned char *data = &(_binary_audio_bin_start[0]);
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// Convert data
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for (int i=0;i<size;i++) *(safe+i) = *(data+i);
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wait_msec(2);
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// Set up control block
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playback_cb.ti = DMA_DEST_DREQ + DMA_PERMAP_1 + DMA_SRC_INC;
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playback_cb.source_ad = SAFE_ADDRESS;
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playback_cb.dest_ad = PWM_LEGACY_BASE + 0x18; // Points to PWM_FIFO
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playback_cb.txfr_len = size * 4; // They're unsigned ints now, not unsigned chars
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playback_cb.stride = 0x00;
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playback_cb.nextconbk = 0x00; // Don't loop
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playback_cb.null1 = 0x00;
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playback_cb.null2 = 0x00;
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wait_msec(2);
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// Enable DMA
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*(pwm+BCM2711_PWM_DMAC) =
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BCM2711_PWM_ENAB + 0x0707; // Bits 0-7 Threshold For DREQ Signal = 1, Bits 8-15 Threshold For PANIC Signal = 0
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*dmae = DMA_EN1;
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*(dma+DMA_CONBLK_AD) = (long)&playback_cb; // checked and correct
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wait_msec(2);
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*(dma+DMA_CS) = DMA_ACTIVE;
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}
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static void audio_init(void)
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{
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@ -94,29 +160,36 @@ void playaudio_cpu()
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void core2_main(void)
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{
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clear_core2(); // Only run once
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clear_core2(); // Only run once
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debugstr("Playing on CPU Core #2... ");
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playaudio_cpu();
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debugstr(" done"); debugcrlf();
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debugstr("Playing on CPU Core #2 using DMA... ");
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playaudio_dma();
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debugstr("done"); debugcrlf();
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debugstr("core2_main() running still... ");
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while (*(dma+DMA_CS) & 0x1) { // Wait for DMA transfer to finish - we could do anything here instead!
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wait_msec(0x47FFFF);
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debugstr("o"); // Print an o roughly every 4.5 seconds
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}
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debugstr(" ----> finished");
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}
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void core1_main(void)
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{
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clear_core1(); // Only run once
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clear_core1(); // Only run once
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debugstr("Playing on CPU Core #1... ");
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playaudio_cpu();
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debugstr(" done"); debugcrlf();
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start_core2(core2_main); // Kick it off on core 2
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start_core2(core2_main); // Kick it off on core 2
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}
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void core0_main(void)
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{
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while (1) {
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wait_msec(0x100000);
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debugstr("x");
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debugstr("x"); // Print an x roughly every 1 second
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}
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}
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@ -128,6 +201,6 @@ void main(void)
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audio_init();
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debugstr("done"); debugcrlf();
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start_core1(core1_main); // Kick it off on core 1
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core0_main(); // Loop endlessly, printing x's
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start_core1(core1_main); // Kick it off on core 1
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core0_main(); // Loop endlessly, printing x's
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}
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