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58 lines
2.1 KiB
C
58 lines
2.1 KiB
C
// ***************************************
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// SCTLR_EL1, System Control Register (EL1), Page 2654 of AArch64-Reference-Manual.
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// ***************************************
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#define SCTLR_RESERVED (3 << 28) | (3 << 22) | (1 << 20) | (1 << 11)
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#define SCTLR_EE_LITTLE_ENDIAN (0 << 25)
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#define SCTLR_EOE_LITTLE_ENDIAN (0 << 24)
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#define SCTLR_I_CACHE_DISABLED (0 << 12)
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#define SCTLR_D_CACHE_DISABLED (0 << 2)
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#define SCTLR_MMU_DISABLED (0 << 0)
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#define SCTLR_MMU_ENABLED (1 << 0)
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#define SCTLR_VALUE_MMU_DISABLED (SCTLR_RESERVED | SCTLR_EE_LITTLE_ENDIAN | SCTLR_I_CACHE_DISABLED | SCTLR_D_CACHE_DISABLED | SCTLR_MMU_DISABLED)
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// ***************************************
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// HCR_EL2, Hypervisor Configuration Register (EL2), Page 2487 of AArch64-Reference-Manual.
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// ***************************************
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#define HCR_RW (1 << 31)
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#define HCR_VALUE HCR_RW
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// ***************************************
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// SCR_EL3, Secure Configuration Register (EL3), Page 2648 of AArch64-Reference-Manual.
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// ***************************************
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#define SCR_RESERVED (3 << 4)
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#define SCR_RW (1 << 10)
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#define SCR_NS (1 << 0)
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#define SCR_VALUE (SCR_RESERVED | SCR_RW | SCR_NS)
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// ***************************************
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// SPSR_EL3, Saved Program Status Register (EL3) Page 389 of AArch64-Reference-Manual.
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// ***************************************
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#define SPSR_MASK_ALL (7 << 6)
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#define SPSR_EL1h (5 << 0)
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#define SPSR_VALUE (SPSR_MASK_ALL | SPSR_EL1h)
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// ***************************************
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// Memory management stuff
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// ***************************************
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#define PAGE_SHIFT 12
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#define TABLE_SHIFT 9
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#define SECTION_SHIFT (PAGE_SHIFT + TABLE_SHIFT)
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#define PAGE_SIZE (1 << PAGE_SHIFT)
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#define SECTION_SIZE (1 << SECTION_SHIFT)
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#define LOW_MEMORY (2 * SECTION_SIZE) // 0x400000
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// ***************************************
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// Timer stuff
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// ***************************************
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#define LOCAL_CONTROL 0xff800000
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#define LOCAL_PRESCALER 0xff800008
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#define OSC_FREQ 54000000
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