mirror of
https://github.com/isometimes/rpi4-osdev
synced 2024-11-09 20:00:40 +00:00
102 lines
2.9 KiB
C
102 lines
2.9 KiB
C
#include "include/fb.h"
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#include "include/io.h"
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#include "include/multicore.h"
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#define PWM_BASE (PERIPHERAL_BASE + 0x20C000 + 0x800) /* PWM1 register base address on RPi4 */
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#define PWM_LEGACY_BASE (LEGACY_BASE + 0x20C000 + 0x800) /* PWM1 register base legacy address on RPi4 */
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#define CLOCK_BASE (PERIPHERAL_BASE + 0x101000)
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#define BCM2711_PWMCLK_CNTL 40
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#define BCM2711_PWMCLK_DIV 41
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#define PM_PASSWORD 0x5A000000
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#define BCM2711_PWM_CONTROL 0
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#define BCM2711_PWM_STATUS 1
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#define BCM2711_PWM_DMAC 2
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#define BCM2711_PWM0_RANGE 4
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#define BCM2711_PWM0_DATA 5
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#define BCM2711_PWM_FIFO 6
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#define BCM2711_PWM1_RANGE 8
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#define BCM2711_PWM1_DATA 9
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#define BCM2711_PWM1_USEFIFO 0x2000 /* Data from FIFO */
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#define BCM2711_PWM1_ENABLE 0x0100 /* Channel enable */
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#define BCM2711_PWM0_USEFIFO 0x0020 /* Data from FIFO */
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#define BCM2711_PWM0_ENABLE 0x0001 /* Channel enable */
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#define BCM2711_PWM_ENAB 0x80000000 /* PWM DMA Configuration: DMA Enable (bit 31 set) */
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#define BCM2711_GAPO2 0x20
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#define BCM2711_GAPO1 0x10
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#define BCM2711_RERR1 0x8
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#define BCM2711_WERR1 0x4
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#define BCM2711_FULL1 0x1
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#define ERRORMASK (BCM2711_GAPO2 | BCM2711_GAPO1 | BCM2711_RERR1 | BCM2711_WERR1)
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volatile unsigned* clk = (void*)CLOCK_BASE;
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volatile unsigned* pwm = (void*)PWM_BASE;
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void audio_init(void)
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{
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gpio_useAsAlt0(40); // Ensure PWM1 is mapped to GPIO 40/41
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gpio_useAsAlt0(41);
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wait_msec(2);
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// Setup clock
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*(clk + BCM2711_PWMCLK_CNTL) = PM_PASSWORD | (1 << 5); // Stop clock
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wait_msec(2);
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int idiv = 2;
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*(clk + BCM2711_PWMCLK_DIV) = PM_PASSWORD | (idiv<<12);
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*(clk + BCM2711_PWMCLK_CNTL) = PM_PASSWORD | 16 | 1; // Osc + Enable
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wait_msec(2);
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// Setup PWM
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*(pwm + BCM2711_PWM_CONTROL) = 0;
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wait_msec(2);
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*(pwm+BCM2711_PWM0_RANGE) = 0x264; // 44.1khz, Stereo, 8-bit (54Mhz / 44100 / 2)
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*(pwm+BCM2711_PWM1_RANGE) = 0x264;
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*(pwm+BCM2711_PWM_CONTROL) =
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BCM2711_PWM1_USEFIFO |
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BCM2711_PWM1_ENABLE |
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BCM2711_PWM0_USEFIFO |
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BCM2711_PWM0_ENABLE | 1<<6;
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}
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void snd_core(void)
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{
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clear_core2();
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int i=0;
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long status;
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extern unsigned char _binary_bin_audio_bin_start[];
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extern unsigned char _binary_bin_audio_bin_size[];
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unsigned int size = (long)&_binary_bin_audio_bin_size;
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unsigned char *data = &(_binary_bin_audio_bin_start[0]);
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// Initialise the audio
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audio_init();
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// Write data out to FIFO and loop infinitely
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while (1) {
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while (i < size) {
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status = *(pwm + BCM2711_PWM_STATUS);
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if (!(status & BCM2711_FULL1)) {
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*(pwm+BCM2711_PWM_FIFO) = *(data + i);
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i++;
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*(pwm+BCM2711_PWM_FIFO) = *(data + i);
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i++;
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}
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if ((status & ERRORMASK)) {
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*(pwm+BCM2711_PWM_STATUS) = ERRORMASK;
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}
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}
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i=0;
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}
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}
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