mirror of
https://github.com/isometimes/rpi4-osdev
synced 2024-11-09 20:00:40 +00:00
259 lines
7 KiB
C
259 lines
7 KiB
C
#include "fb.h"
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#include "io.h"
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#include "multicore.h"
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#define PWM_BASE (PERIPHERAL_BASE + 0x20C000 + 0x800) /* PWM1 register base address on RPi4 */
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#define PWM_LEGACY_BASE (LEGACY_BASE + 0x20C000 + 0x800) /* PWM1 register base legacy address on RPi4 */
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#define CLOCK_BASE (PERIPHERAL_BASE + 0x101000)
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#define DMA_BASE (PERIPHERAL_BASE + 0x007100) /* DMA register base address */
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#define DMA_ENABLE (DMA_BASE + 0xFF0) /* DMA global enable bits */
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#define BCM2711_PWMCLK_CNTL 40
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#define BCM2711_PWMCLK_DIV 41
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#define PM_PASSWORD 0x5A000000
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#define BCM2711_PWM_CONTROL 0
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#define BCM2711_PWM_STATUS 1
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#define BCM2711_PWM_DMAC 2
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#define BCM2711_PWM0_RANGE 4
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#define BCM2711_PWM0_DATA 5
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#define BCM2711_PWM_FIFO 6
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#define BCM2711_PWM1_RANGE 8
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#define BCM2711_PWM1_DATA 9
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#define BCM2711_PWM1_USEFIFO 0x2000 /* Data from FIFO */
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#define BCM2711_PWM1_ENABLE 0x0100 /* Channel enable */
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#define BCM2711_PWM0_USEFIFO 0x0020 /* Data from FIFO */
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#define BCM2711_PWM0_ENABLE 0x0001 /* Channel enable */
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#define BCM2711_PWM_ENAB 0x80000000 /* PWM DMA Configuration: DMA Enable (bit 31 set) */
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#define BCM2711_GAPO2 0x20
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#define BCM2711_GAPO1 0x10
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#define BCM2711_RERR1 0x8
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#define BCM2711_WERR1 0x4
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#define BCM2711_FULL1 0x1
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#define ERRORMASK (BCM2711_GAPO2 | BCM2711_GAPO1 | BCM2711_RERR1 | BCM2711_WERR1)
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#define DMA_CS 0 /* Control/status register offset for DMA channel 0 */
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#define DMA_CONBLK_AD 1
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#define DMA_EN1 1 << 1 /* Enable DMA engine 1 */
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#define DMA_ACTIVE 1 /* Active bit set */
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#define DMA_DEST_DREQ 0x40 /* Use DREQ to pace peripheral writes */
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#define DMA_PERMAP_1 0x10000 /* PWM1 peripheral for DREQ */
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#define DMA_SRC_INC 0x100 /* Increment source address */
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volatile unsigned* clk = (void*)CLOCK_BASE;
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volatile unsigned* pwm = (void*)PWM_BASE;
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volatile unsigned* dma = (void*)DMA_BASE;
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volatile unsigned* dmae = (void*)DMA_ENABLE;
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volatile unsigned* safe = (void*)SAFE_ADDRESS;
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struct dma_cb {
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unsigned int ti;
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unsigned int source_ad;
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unsigned int dest_ad;
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unsigned int txfr_len;
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unsigned int stride;
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unsigned int nextconbk;
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unsigned int null1;
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unsigned int null2;
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} __attribute__((aligned(32)));
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struct dma_cb playback_cb;
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static void playaudio_dma(void)
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{
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extern unsigned char _binary_audio_bin_start[];
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extern unsigned char _binary_audio_bin_size[];
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unsigned int size = (long)&_binary_audio_bin_size;
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unsigned char *data = &(_binary_audio_bin_start[0]);
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// Convert data
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for (int i=0;i<size;i++) *(safe+i) = *(data+i);
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wait_msec(2);
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// Set up control block
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playback_cb.ti = DMA_DEST_DREQ + DMA_PERMAP_1 + DMA_SRC_INC;
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playback_cb.source_ad = SAFE_ADDRESS;
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playback_cb.dest_ad = PWM_LEGACY_BASE + 0x18; // Points to PWM_FIFO
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playback_cb.txfr_len = size * 4; // They're unsigned ints now, not unsigned chars
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playback_cb.stride = 0x00;
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playback_cb.nextconbk = 0x00; // Don't loop
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playback_cb.null1 = 0x00;
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playback_cb.null2 = 0x00;
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wait_msec(2);
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// Enable DMA
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*(pwm+BCM2711_PWM_DMAC) =
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BCM2711_PWM_ENAB + 0x0707; // Bits 0-7 Threshold For DREQ Signal = 1, Bits 8-15 Threshold For PANIC Signal = 0
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*dmae = DMA_EN1;
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*(dma+DMA_CONBLK_AD) = (long)&playback_cb; // checked and correct
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wait_msec(2);
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*(dma+DMA_CS) = DMA_ACTIVE;
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}
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static void audio_init(void)
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{
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gpio_useAsAlt0(40); // Ensure PWM1 is mapped to GPIO 40/41
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gpio_useAsAlt0(41);
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wait_msec(2);
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// Setup clock
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*(clk + BCM2711_PWMCLK_CNTL) = PM_PASSWORD | (1 << 5); // Stop clock
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wait_msec(2);
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int idiv = 2;
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*(clk + BCM2711_PWMCLK_DIV) = PM_PASSWORD | (idiv<<12);
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*(clk + BCM2711_PWMCLK_CNTL) = PM_PASSWORD | 16 | 1; // Osc + Enable
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wait_msec(2);
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// Setup PWM
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*(pwm + BCM2711_PWM_CONTROL) = 0;
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wait_msec(2);
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*(pwm+BCM2711_PWM0_RANGE) = 0x264; // 44.1khz, Stereo, 8-bit (54Mhz / 44100 / 2)
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*(pwm+BCM2711_PWM1_RANGE) = 0x264;
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*(pwm+BCM2711_PWM_CONTROL) =
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BCM2711_PWM1_USEFIFO |
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BCM2711_PWM1_ENABLE |
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BCM2711_PWM0_USEFIFO |
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BCM2711_PWM0_ENABLE | 1<<6;
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}
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void playaudio_cpu()
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{
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int i=0;
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long status;
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extern unsigned char _binary_audio_bin_start[];
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extern unsigned char _binary_audio_bin_size[];
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unsigned int size = (long)&_binary_audio_bin_size;
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unsigned char *data = &(_binary_audio_bin_start[0]);
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// Write data out to FIFO
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while (i < size) {
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status = *(pwm + BCM2711_PWM_STATUS);
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if (!(status & BCM2711_FULL1)) {
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*(pwm+BCM2711_PWM_FIFO) = *(data + i);
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i++;
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*(pwm+BCM2711_PWM_FIFO) = *(data + i);
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i++;
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}
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if ((status & ERRORMASK)) {
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*(pwm+BCM2711_PWM_STATUS) = ERRORMASK;
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}
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}
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}
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void initProgress(void)
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{
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drawRect(0, 0, 301, 50, 0x0f, 0);
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drawString(309, 21, "Core 0", 0x0f, 1);
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drawRect(0, 60, 301, 110, 0x0f, 0);
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drawString(309, 81, "Core 1", 0x0f, 1);
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drawRect(0, 120, 301, 170, 0x0f, 0);
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drawString(309, 141, "Core 2", 0x0f, 1);
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drawRect(0, 180, 301, 230, 0x0f, 0);
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drawString(309, 201, "Core 3", 0x0f, 1);
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}
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void drawProgress(unsigned int core, unsigned int val) {
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unsigned char col = (core + 1) + ((core + 1) << 4);
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// val should be 0-100
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if (val == 0) drawRect(1, (60 * core) + 1, 300, (60 * core) + 49, 0x00, 1);
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if (val > 0) drawRect(1, (60 * core) + 1, (val * 3), (60 * core) + 49, col, 1);
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}
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void core3_main(void)
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{
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unsigned int core3_val = 0;
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clear_core3(); // Only run once
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while (1) {
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wait_msec(0x3FFFF);
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drawProgress(3, core3_val);
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if (core3_val < 100) core3_val++;
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}
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}
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void core2_main(void)
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{
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unsigned int core2_val = 0;
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clear_core2(); // Only run once
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debugstr("Playing on CPU Core #2 using DMA... ");
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playaudio_dma();
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debugstr("done"); debugcrlf();
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debugstr("core2_main() running still... ");
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while (*(dma+DMA_CS) & 0x1) { // Wait for DMA transfer to finish - we could do anything here instead!
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wait_msec(0x7FFFF);
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drawProgress(2, core2_val);
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if (core2_val < 100) core2_val++;
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}
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debugstr("done");
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drawProgress(2, 100);
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}
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void core1_main(void)
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{
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clear_core1(); // Only run once
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drawProgress(1, 50);
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debugstr("Playing on CPU Core #1... ");
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playaudio_cpu();
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debugstr("done"); debugcrlf();
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drawProgress(1, 100);
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start_core2(core2_main); // Kick it off on core 2
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}
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void core0_main(void)
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{
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unsigned int core0_val = 0;
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while (1) {
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wait_msec(0x100000);
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drawProgress(0, core0_val);
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if (core0_val < 100) core0_val++;
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}
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}
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void main(void)
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{
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fb_init();
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initProgress();
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unsigned int i=0;
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while (i++<30) debugcrlf();
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debugstr("Initialising audio unit... ");
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audio_init();
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debugstr("done"); debugcrlf();
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start_core3(core3_main); // Kick it off on core 3
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start_core1(core1_main); // Kick it off on core 1
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core0_main(); // Loop endlessly
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}
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